This invention relates to an improvement of a device for detecting overlap of operands in a memory, which operands are specified by a store instruction and a fetch instruction, respectively, in a pipeline control data processing system.
In a pipeline control data processing system, the effective instruction processing time is minimized by executing a plurality of instructions in parallel. Although the pipeline control data processing system performs parallel processing of several instructions, the sequence for executing such instructions must be guaranteed. According to the pipeline control, when a store instruction for writing a data item in a memory is followed by a fetch instruction for reading a data item from the memory, a fetch request due to the fetch instruction following the store instruction may take place before a store request by the store instruction. To guarantee the sequence for executing the instructions in this situation, the system checks whether or not the memory area to be changed by the preceding store instruction overlaps with the memory area from which a data item is read by the succeeding fetch instruction. If it is found that they overlap each other, the processing of the fetch instruction must be set to and retained in the wait state until the processing of the preceding store instruction is completed. However, such an overlap between a store instruction and a fetch instruction is detected according to the memory access width in the conventional art, hence an overlap is detected even when there does not actually exist any overlap, thereby degrading the advantage of the pipeline control. For example, in a data processing system whose memory access width is eight bytes, when the preceding store instruction changes the first four bytes in an 8-byte memory boundary and the succeeding fetch instruction reads the last four bytes from the 8-byte memory boundary, an overlap is detected although an overlap does not actually exist. Since a reading of a data item from the memory by the succeeding fetch instruction is delayed until the preceding instruction completely stores a data item in the memory when the overlap is detected, the pipeline cannot be operated properly and the performance is deteriorated.